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Freescale Semiconductor /MK21D5WS /PORTA /DFCR

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Interpret as DFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CS 0RESERVED

CS=0

Description

Digital Filter Clock Register

Fields

CS

Clock Source

0 (0): Digital filters are clocked by the bus clock.

1 (1): Digital filters are clocked by the 1 kHz LPO clock.
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data